1. Field of the Invention
The present invention relates generally to a shift register, and is directed more particularly to a shift register formed of an IIL (integrated injection logic) or MTL (merged transistor logic).
2. Description of the Prior Art
A prior art IIL is fundamentally formed as shown in FIG. 1. In FIG. 1, N0 designates, for example, an N-conductivity type semiconductor substrate, P1 and P2 P-conductivity type regions, which are respectively formed on one of the major surfaces of substrate N0, and N1 to N3 N-conductivity type regions which are respectively formed in the region P2. Electrodes (terminals) I, B and C1 to C3 are connected to the regions P1, P2 and N1 to N3, respectively.
In the IIL shown in FIG. 1, the region P1-substrate N0-region P2 form a transistor Q1 as shown in FIG. 2, and the substrate N0-region P2-regions N1 to N3 form an NPN-type transistor Q2 of a multi-collector type as shown in FIG. 2. In this case, both transistors Q1 and Q2 are connected with each other as shown in FIG. 2.
With the IIL shown in FIG. 1 or FIG. 2, when a voltage +V.sub.EE is applied to the electrode I, the transistor Q1 operates as a constant current bias source. Therefore, the transistor Q2 operates as an inverter of an open-collector type. Further, when the voltage +V.sub.EE applied to the electrode I is turned ON and OFF, the transistor Q2 operates as a gate.
In the following description, the IIL described above will be symbolized as shown in FIG. 3 for the sake of brevity.
In the case where the above IILs are used to make a shift register of the synchronous type in the art, if the shift register is of the 2-phase clock type, the IILs are made as an IC (integrated circuit) with the connection shown in FIG. 4, while if the shift register is of the single-phase type, the IILs are made as an IC with the connection shown in FIG. 5. Each of FIGS. 4 and 5 shows a shift register of 2-bits.
The prior art shift register shown in FIG. 4 requires ten IILs for 1 bit, and the shift register shown in FIG. 5 requires seven IILs for 1 bit. Therefore, the areas of both chips forming the shift registers shown in FIGS. 4 and 5 will large, which is disadvantageous for making them as an IC.
Further, it is necessary for both prior art shift registers to supply a clock pulse to each of the bits, so that a complicated wiring pattern is required in each of the shift registers, which results in that the integration ratio deteriorates and hence both the shift registers result in disadvantages when made into an IC.
Also, it is required that each of clock pulse sources drives each of the bits in the shift register.